This invention generally relates to methods for forming blocking layers and more particularly to a method for forming a blocking layer to reduce a diffusion rate of a chemical species thereby improving a photolithographic process.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density on the chip. One of the limiting factors in the continuing evolution toward the smaller device size and higher density has been the interconnect area needed to route interconnect lines between devices. As a way to overcome such limitation, multilayer interconnection systems with increasingly smaller features have been implemented using shared interconnect lines between two or more layers.
The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, photolithography, etching, and planarization.
One such process for forming a series of interconnected multiple layer devices, for example, is a damascene or dual damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ a series of photolithographic masking and etching steps, typically by a reactive ion etch (RIE). One exemplary process, for example, is known in the art as a via-first-trench last process. Typically a conventional photolithographic process using a photoresist layer is first used to pattern and expose an etching mask which is used for etching via openings through an insulating inter-metal dielectric (IMD) layer. Subsequently a similar process is used to define trench openings for metal interconnect lines in an insulating metallization layer that are formed substantially over the via openings. The via opening and trench openings are subsequently filled with metal to form metallization vias and metal interconnect lines, respectively. The surface may then be planarized by conventional techniques, such as chemical mechanical polishing (CMP) to better define the metal interconnect lines and prepare the substrate for further processing.
Referring to FIG. 1, typically, an insulating layer (IMD) 12 layer is formed over a metallization layer 10. Prior to forming the IMD layer 12, an etch stop layer 14A, for example, silicon nitride (SiN) or silicon carbide (SiC) is formed over the metallization layer 10. Another etch layer stop layer 14B is then formed over IMD layer 12. Prior to forming via openings 18A, 18B, and 18C, dielectric anti-reflective coating (DARC) layer 16 is formed over the etching stop layer 14B prior to depositing a photoresist coating 20 for carrying out a photolithographic process used for patterning and subsequently etching by, for example, a reactive ion etch (RIE) the via openings 18A, 18B, and 18C. The DARC layer 16 reduces the effect of light reflection undesirably exposing the photoresist overlayer 20 used for defining via openings 18A, 18B, and 18C. Light reflection (scattering) from, for example, the IMD layer 12 surface, etching stop layer 14B surface, and their respective interfaces, can cause undesired light exposure of the overlying photoresist layer 20 during photolithographic masking and patterning steps in the formation of via openings 18A, 18B, and 18C. As a result, upon development and removal of the exposed photoresist the phenomenon of undercutting (removing photoresist exposed by reflected light at the base of the photoresist layer) will detrimentally affect the design integrity of the manufactured device.
As feature sizes in etching process have become increasingly smaller, photolithographic processes have been required to use photoresist activating light (radiation) of smaller wavelength. Typically a deep ultraviolet (DUV) activating light source with wavelength less than about 250, but more typically, from about 193 nm to about 230 nm is used. Exemplary DUV photoresists used, for example, have included, PMMA and polybutene sulfone.
Many processes use a metal nitride as a DARC (dielectric anti-reflective coating) such as silicon oxynitride (SiON), silicon nitride SiN, or titanium nitride TiN. Typically, the method of choice for depositing these metal nitride layers is a CVD process where for example, a metal-organic precursor together with nitrogen (and oxygen in the case of SiON) is deposited on a substrate surface, to form a metal nitride. Silicon oxynitride DARC, has been widely used for DUV (deep ultraviolet) lithography because of its tunable refractive index and high etch selectivity to resist.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use or application of metal nitride films such as SiN as etch stops and, for example, silicon oxynitride as a DARC. For example, nitrogen radicals created due to the presence of nitrogen containing species, such as amines, interfere, with chemically amplified resists by neutralizing the acid catalyst, and rendering that portion of the photoresist insoluble in the developer. As a result, residual photoresist may a remain on the edges and walls of features, affecting subsequent etching or metal filling processes and altering design constraints.
Another aspect of advances in semiconductor device processing technology that exacerbates the problem is the increasing use of low-k (low dielectric constant)insulating materials that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials have become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. An exemplary low-k material is, for example, carbon doped silicon dioxide (C-oxide) which has a dielectric of about 3 or lower and density of about 1.3 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS). A shortcoming of porous low-k materials is that they readily absorb and provide diffusion pathways for chemical species.
As a result, amine and nitrogen-containing species remaining in, for example, a SiON DARC, may readily diffuse into an underlying or overlying IMD layer, thereby becoming potentially available for causing interfering effects with a subsequent photoresist process. The contaminating nitrogen-containing species may diffuse back out of the IMD layer during a photoresist process causing residual photoresist to remain after development thereby altering resist profiles by, for example, remaining deposited on feature edges and sidewalls.
There is therefore a need in the semiconductor processing art to develop a method whereby residual nitrogen-containing species in for example, DARC layers, are prevented from diffusing into insulating materials, for example, IMD layers, especially where the IMD layers include a low-k material.
It is therefore an object of the invention to provide a method whereby residual nitrogen-containing species in for example, DARC layers, are blocked from diffusing into insulating materials, for example, IMD layers, especially where the insulating material is a low-k material while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a blocking layer to reduce a diffusion rate of a chemical species thereby improving a photolithographic process.
In a first embodiment according to the present invention, a method if provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of: providing an insulating layer comprising a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of a chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.
In related embodiments, the target surface comprises a silicon oxide. Further, the silicon oxide further comprises a low-k material with a dielectric constant of less than about 3.5. Further yet, the low-k material includes carbon doped silicon dioxide.
In another related embodiment, the at least one metal ergo nitride layer includes an etch stop layer and a dielectric anti-reflectance coating (DARC) layer. Further, the etch stop layer is selected from the group consisting of silicon nitride, silicon oxynitride, and titanium nitride. Further yet, the DARC layer is selected from the group consisting of silicon nitride, silicon oxynitride, and titanium nitride.
In another related embodiment, the photolithographic process comprises photogeneration of a nitrogen containing radical species within a photoresist.
In yet another related embodiment, the density increase comprises a physical process including ions in the RF generated plasma impacting on the target surface. Further, the physical process is carried out prior to a chemical process whereby ions in the RF generated plasma chemically react with the target surface.
In another embodiment, the density increase comprises a chemical process whereby ions in the RF generated plasma chemically react with the target surface. Further, the ions include oxygen ions and the target surface includes silicon oxide whereby oxygen is incorporated into the target surface.